Invention Grant
- Patent Title: Modeling electrical interconnections in three-dimensional structures
- Patent Title (中): 在三维结构中建模电互连
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Application No.: US12288616Application Date: 2008-10-22
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Publication No.: US08352232B2Publication Date: 2013-01-08
- Inventor: Ki Jin Han , Madhavan Swaminathan
- Applicant: Ki Jin Han , Madhavan Swaminathan
- Applicant Address: US GA Atlanta
- Assignee: Georgia Tech Research Corporation
- Current Assignee: Georgia Tech Research Corporation
- Current Assignee Address: US GA Atlanta
- Agency: Bockhop & Associates, LLC
- Agent Bryan W. Bockhop
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455

Abstract:
Disclosed are apparatus, methods and software that implement a partial element equivalent circuit (PEEC) method having global basis functions on cylindrical coordinates to determine wide-band resistance, inductance, capacitance, and conductance from a large number of three-dimensional interconnections in order to provide for the electrical design of system-in-package (SIP) modules, and the like. The apparatus, methods and software use a modal equivalent network from mixed potential integral equation with cylindrical conduction and accumulation mode basis functions, which reduces the matrix size for large three-dimensional interconnection problems. Combined with these modal basis functions, the mixed potential integral equations describe arbitrary skin and proximity effects, and allow determination of partial impedance and admittance values. Additional enhancement schemes further reduces the cost for computing the partial inductances. Therefore, the apparatus, methods and software can be used to construct accurate models of a large number of three-dimensional interconnection structures, including more than 100 bonding wires used for stacking integrated circuit chips, through-silicon via interconnections, and the like.
Public/Granted literature
- US20100094609A1 Modeling electrical interconnections in three-dimensional structures Public/Granted day:2010-04-15
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