Invention Grant
US08352385B2 Low-power analog-circuit architecture for decoding neural signals
有权
用于解码神经信号的低功耗模拟电路架构
- Patent Title: Low-power analog-circuit architecture for decoding neural signals
- Patent Title (中): 用于解码神经信号的低功耗模拟电路架构
-
Application No.: US12127380Application Date: 2008-05-27
-
Publication No.: US08352385B2Publication Date: 2013-01-08
- Inventor: Benjamin I. Rapoport , Rahul Sarpeshkar , Woradorn Wattanapanitch
- Applicant: Benjamin I. Rapoport , Rahul Sarpeshkar , Woradorn Wattanapanitch
- Applicant Address: US MA Cambridge
- Assignee: Massachusetts Institute of Technology
- Current Assignee: Massachusetts Institute of Technology
- Current Assignee Address: US MA Cambridge
- Agency: Gesmer Updegrove LLP
- Main IPC: G06F15/18
- IPC: G06F15/18

Abstract:
A microchip for performing a neural decoding algorithm is provided. The microchip is implemented using ultra-low power electronics. Also, the microchip includes a tunable neural decodable filter implemented using a plurality of amplifiers, a plurality of parameter learning filters, a multiplier, a gain and time-constant biasing circuits; and analog memory. The microchip, in a training mode, learns to perform an optimized translation of a raw neural signal received from a population of cortical neurons into motor control parameters. The optimization being based on a modified gradient descent least square algorithm wherein update for a given parameter in a filter is proportional to an averaged product of an error in the final output that the filter affects and a filtered version of its input. The microchip, in an operational mode, issues commands to controlling a device using learned mappings.
Public/Granted literature
- US20080294579A1 LOW-POWER ANALOG-CIRCUIT ARCHITECTURE FOR DECODING NEURAL SIGNALS Public/Granted day:2008-11-27
Information query