An integer division circuit with allowable error is described, what a signal processing apparatus includes a pointer, a first left shifter, a second left shifter, a subtractor, a multiplier, and a right shifter. The pointer searches for a most significant non-zero bit of a divisor and outputs a most significant byte value. The first left shifter performs a shift operation according to the most significant byte value, so as to generate a first exponential coefficient. The second left shifter performs a shift operation according to the most significant byte value, so as to generate a second exponential coefficient. The subtractor calculates a multiplier factor according to the divisor, the first exponential coefficient, and the second exponential coefficient and outputs the multiplier factor to the multiplier. The multiplier multiplies an input value with the multiplier factor and outputs a result to the right shifter. The right shifter outputs a calculation result.