Invention Grant
- Patent Title: Error addition apparatus
- Patent Title (中): 错误添加装置
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Application No.: US12683072Application Date: 2010-01-06
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Publication No.: US08352836B2Publication Date: 2013-01-08
- Inventor: Takashi Furuya
- Applicant: Takashi Furuya
- Applicant Address: JP Atsugi-shi
- Assignee: Anritsu Corporation
- Current Assignee: Anritsu Corporation
- Current Assignee Address: JP Atsugi-shi
- Agency: Greer, Burns & Crain, Ltd.
- Priority: JP2009-002485 20090108
- Main IPC: H03M13/33
- IPC: H03M13/33 ; H03M13/53

Abstract:
An error addition apparatus receives a data signal D having a frame format having a specific signal inserted into its front, adds errors to the data signal D, and outputs a resulting signal. The apparatus has an error addition regulation unit for receiving a frame synchronization signal F, indicative of a timing at which the front of the frame of the data signal has been inputted, and regulating the errors such that the errors are added to positions other than a region of the specific signal. Accordingly, errors are not added to a specific signal.
Public/Granted literature
- US20100174971A1 ERROR ADDITION APPARATUS Public/Granted day:2010-07-08
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