Invention Grant
- Patent Title: Circuit topology recognition and circuit partitioning
- Patent Title (中): 电路拓扑识别和电路分区
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Application No.: US13235153Application Date: 2011-09-16
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Publication No.: US08352893B1Publication Date: 2013-01-08
- Inventor: Pole Shang Lin , Tamer Raed Fahim Riad , Kuei Shan Wen
- Applicant: Pole Shang Lin , Tamer Raed Fahim Riad , Kuei Shan Wen
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Aspects of the invention relate to circuit topology recognition and circuit partitioning. In various embodiments of the invention, diode-connected transistors can be identified in a circuit netlist based on the unique structure. From the diode-connected transistors, current mirrors can be found. The current mirrors may be employed for locating differential pairs used in the input stage of operational amplifiers and for locating supply voltage and ground nodes in the netlist. The subcircuits that are strongly connected due to feedback loops of operational amplifiers in the circuit can then be identified and grouped together for circuit analysis and simulation.
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