Aspects of the disclosure provide a speed monitor circuit. The speed monitor circuit monitors a circuit speed in a momentary manner. In addition, the speed monitor circuit consumes a relatively small silicon area. The speed monitor circuit includes a ring oscillator module, an edge capture module, and a controller module. The ring oscillator module has a plurality of stages, and is configured to start oscillating in response to an enable signal. The edge capture module is configured to capture a target edge of a signal propagating in the ring oscillator module at a stage of the ring oscillator module. The controller module is configured to receive a first edge and a second edge of a clock signal, provide the enable signal to the ring oscillator module based on the first edge to enable oscillating, and compare timings of the second edge and the captured target edge to detect the circuit speed.