Invention Grant
- Patent Title: Pattern evaluation system, pattern evaluation method and semiconductor device manufacturing method
- Patent Title (中): 模式评估系统,模式评估方法和半导体器件制造方法
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Application No.: US12847716Application Date: 2010-07-30
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Publication No.: US08355560B2Publication Date: 2013-01-15
- Inventor: Tadashi Mitsui
- Applicant: Tadashi Mitsui
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2010-2173 20100107
- Main IPC: G06K9/00
- IPC: G06K9/00 ; C09K19/00

Abstract:
In accordance with an embodiment, a pattern evaluation system includes an image acquisition unit, a plurality of image processing units, and a control unit which controls the plurality of image processing units. The image acquisition unit loads a series of images of a pattern to be evaluated. The images are acquired at a first speed. The plurality of image processing units process the series of images at a second speed and then output a result of the evaluation of the pattern to be evaluated. The control unit acquires the first and second speeds, estimates the number of the image processing units which allow the time for acquiring the series of images to be substantially the same as the time for processing the series of images, and allocates the estimated image processing units to the processing of the series of images.
Public/Granted literature
- US20110164807A1 PATTERN EVALUATION SYSTEM, PATTERN EVALUATION METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD Public/Granted day:2011-07-07
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