Invention Grant
- Patent Title: Plasma display panel having low residual stress
- Patent Title (中): 等离子显示屏具有低残留应力
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Application No.: US12866267Application Date: 2010-03-11
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Publication No.: US08362680B2Publication Date: 2013-01-29
- Inventor: Kazuhiro Morioka , Morio Fujitani , Hirofumi Higashi , Shinsuke Yoshida , Akira Kawase , Tatsuo Mifune
- Applicant: Kazuhiro Morioka , Morio Fujitani , Hirofumi Higashi , Shinsuke Yoshida , Akira Kawase , Tatsuo Mifune
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: JP2009-060500 20090313
- International Application: PCT/JP2010/001733 WO 20100311
- International Announcement: WO2010/103836 WO 20100916
- Main IPC: H01J1/62
- IPC: H01J1/62

Abstract:
In a plasma display panel, in which an area percentage of the display electrodes in an area of an image display region of the front panel is expressed by a longitudinal axis, and a difference between a coefficient of expansion of the front substrate from room temperature to 300° C. and a coefficient of expansion of the dielectric layer from room temperature to 300° C. is expressed by a lateral axis, the difference between the coefficients of expansion and the area percentage stay within a region formed by connecting coordinates (35×10−7/° C., 60%), coordinates (8×10−7/° C., 60%), coordinates (5×10−7/° C., 40%), and coordinates (23×10−7/° C., 40%) in the mentioned order with a straight line where the straight line is included.
Public/Granted literature
- US20110062854A1 PLASMA DISPLAY PANEL Public/Granted day:2011-03-17
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