发明授权
- 专利标题: Phase locked loop circuit and control method thereof
- 专利标题(中): 锁相环电路及其控制方法
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申请号: US13041084申请日: 2011-03-04
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公开(公告)号: US08368438B2公开(公告)日: 2013-02-05
- 发明人: Manabu Furuta
- 申请人: Manabu Furuta
- 申请人地址: JP Kanagawa
- 专利权人: Renesas Electronics Corporation
- 当前专利权人: Renesas Electronics Corporation
- 当前专利权人地址: JP Kanagawa
- 代理机构: Sughrue Mion, PLLC
- 优先权: JP2010-048964 20100305
- 主分类号: H03L7/06
- IPC分类号: H03L7/06
摘要:
A phase locked loop circuit according to the present invention includes a selector that selects an input clock, a 1/m frequency divider that divides a frequency of the input clock, a 1/n frequency divider that divides a frequency of a feedback clock, a phase difference detector, a first voltage controlled oscillator that includes a first voltage holding circuit, a second voltage controlled oscillator that includes a second voltage holding circuit, and a selection circuit that outputs any output of the first and second voltage controlled oscillators as an output clock and outputs any output of the first and second voltage controlled oscillators as a feedback clock. The input clock is switched when the voltage controlled oscillator in a holding mode generates the output clock and the voltage controlled oscillator in a normal mode generates the feedback clock.
公开/授权文献
- US20110215846A1 PHASE LOCKED LOOP CIRCUIT AND CONTROL METHOD THEREOF 公开/授权日:2011-09-08
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