Invention Grant
US08373209B2 Semiconductor device having D mode JFET and E mode JFET and method for manufacturing the same
有权
具有D型JFET和E型JFET的半导体器件及其制造方法
- Patent Title: Semiconductor device having D mode JFET and E mode JFET and method for manufacturing the same
- Patent Title (中): 具有D型JFET和E型JFET的半导体器件及其制造方法
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Application No.: US12974516Application Date: 2010-12-21
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Publication No.: US08373209B2Publication Date: 2013-02-12
- Inventor: Rajesh Kumar Malhan , Naohiro Sugiyama
- Applicant: Rajesh Kumar Malhan , Naohiro Sugiyama
- Applicant Address: JP Kariya
- Assignee: DENSO CORPORATION
- Current Assignee: DENSO CORPORATION
- Current Assignee Address: JP Kariya
- Agency: Posz Law Group, PLC
- Priority: JP2009-294801 20091225
- Main IPC: H01L29/12
- IPC: H01L29/12

Abstract:
A semiconductor device includes: a substrate; and depletion and enhancement mode JFETs. The depletion mode JFET includes: a concavity on the substrate; a channel layer in the concavity; a first gate region on the channel layer; first source and drain regions on respective sides of the first gate region in the channel layer; first gate, source and drain electrodes. The enhancement mode JFET includes: a convexity on the substrate; the channel layer on the convexity; a second gate region on the channel layer; second source and drain regions on respective sides of the second gate region in the channel layer; second gate, source and drain electrodes. A thickness of the channel layer in the concavity is larger than a thickness of the channel layer on the convexity.
Public/Granted literature
- US20110156053A1 SEMICONDUCTOR DEVICE HAVING D MODE JFET AND E MODE JFET AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2011-06-30
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