Invention Grant
US08379788B2 Systems and methods for performing parallel digital phase-locked-loop
有权
用于执行并行数字锁相环的系统和方法
- Patent Title: Systems and methods for performing parallel digital phase-locked-loop
- Patent Title (中): 用于执行并行数字锁相环的系统和方法
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Application No.: US12818158Application Date: 2010-06-18
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Publication No.: US08379788B2Publication Date: 2013-02-19
- Inventor: Junquiang Hu , Tyrone Kwok , Ting Wang
- Applicant: Junquiang Hu , Tyrone Kwok , Ting Wang
- Applicant Address: US NJ Princeton
- Assignee: NEC Laboratories America, Inc.
- Current Assignee: NEC Laboratories America, Inc.
- Current Assignee Address: US NJ Princeton
- Agent Joseph Kolodka; Bao Tran
- Main IPC: H03D3/24
- IPC: H03D3/24
Abstract:
A parallel phase locked loop (PLL) system includes a first chain of a plurality of pre-locking PLLs that operates from a free-run state to a locked state; and a second chain of a plurality of PLLs to work from the locked-state to recover signal output.
Public/Granted literature
- US20110310998A1 SYSTEMS AND METHODS FOR PERFORMING PARALLEL DIGITAL PHASE-LOCKED-LOOP Public/Granted day:2011-12-22
Information query
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