Invention Grant
- Patent Title: Technique for fast power estimation using probabilistic analysis of combinational logic
- Patent Title (中): 使用组合逻辑概率分析的快速功率估计技术
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Application No.: US12610194Application Date: 2009-10-30
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Publication No.: US08380656B2Publication Date: 2013-02-19
- Inventor: Krishnan Sundaresan , Wei-Lun Hung , Jaewon Oh , Robert E. Mains
- Applicant: Krishnan Sundaresan , Wei-Lun Hung , Jaewon Oh , Robert E. Mains
- Applicant Address: US CA Redwood City
- Assignee: Oracle America, Inc.
- Current Assignee: Oracle America, Inc.
- Current Assignee Address: US CA Redwood City
- Agency: Osha Liang LLP
- Main IPC: G06F15/00
- IPC: G06F15/00 ; G06F15/18 ; G06F17/50

Abstract:
A method for computing power consumption includes querying a software database for a key node and a gate comprising an input port, connected to the key node, and an output port. The software database is created from a net list associated with a design. The method includes calculating a probability of activity level at the output port based on a predetermined activity level at the key node, and querying the software database for next gate comprising a next input port, connected to the previous output port, and a next output port. The method includes calculating a probability of activity level at the next output port based on the probability of activity level at the previous output port. The method includes computing a sub-circuit gate power by sum of power of all the gates based on the probability of activity level at output ports of the gates.
Public/Granted literature
- US20110106748A1 TECHNIQUE FOR FAST POWER ESTIMATION USING PROBABILISTIC ANALYSIS OF COMBINATIONAL LOGIC Public/Granted day:2011-05-05
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