发明授权
- 专利标题: High-performance ingress buffer for a packet switch
- 专利标题(中): 用于分组交换机的高性能入口缓冲区
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申请号: US12630811申请日: 2009-12-03
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公开(公告)号: US08391302B1公开(公告)日: 2013-03-05
- 发明人: Raghunath Reddy Kommidi , David Alan Brown
- 申请人: Raghunath Reddy Kommidi , David Alan Brown
- 申请人地址: US CA San Jose
- 专利权人: Integrated Device Technology, Inc.
- 当前专利权人: Integrated Device Technology, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Glass & Associates
- 代理商 Kenneth Glass; Stanley J. Pawlik
- 主分类号: G01R31/08
- IPC分类号: G01R31/08 ; G06F11/00 ; G08C15/00 ; H04J1/16 ; H04J3/14 ; H04L1/00 ; H04L12/26 ; H04L12/28 ; H04L12/56
摘要:
A packet switch includes ingress ports, each of which contains a random access memory having a storage capacity for storing data. An ingress controller of the packet switch allocates the storage capacity of each random access memory among transaction types of packets by allocating credits to each of the transactions types for the random access memory. Each ingress port accepts packets based on the transaction types of the packets and the credits of the random access memory in the ingress port. Moreover, the ingress port stores accepted packets in the random access memory of the ingress port. In further embodiments, the ingress controller dynamically reallocates the credits of the random access memory in the ingress port during operation of the packet switch.
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