发明授权
US08391302B1 High-performance ingress buffer for a packet switch 有权
用于分组交换机的高性能入口缓冲区

High-performance ingress buffer for a packet switch
摘要:
A packet switch includes ingress ports, each of which contains a random access memory having a storage capacity for storing data. An ingress controller of the packet switch allocates the storage capacity of each random access memory among transaction types of packets by allocating credits to each of the transactions types for the random access memory. Each ingress port accepts packets based on the transaction types of the packets and the credits of the random access memory in the ingress port. Moreover, the ingress port stores accepted packets in the random access memory of the ingress port. In further embodiments, the ingress controller dynamically reallocates the credits of the random access memory in the ingress port during operation of the packet switch.
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