Invention Grant
- Patent Title: Electronic device, integrated circuit and method for selecting of an optimal sampling clock phase
- Patent Title (中): 电子设备,集成电路和选择最佳采样时钟相位的方法
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Application No.: US12522047Application Date: 2007-01-09
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Publication No.: US08391415B2Publication Date: 2013-03-05
- Inventor: Paul Kelleher , Diarmuid McSwiney , Conor O'Keeffe
- Applicant: Paul Kelleher , Diarmuid McSwiney , Conor O'Keeffe
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- International Application: PCT/EP2007/050188 WO 20070109
- International Announcement: WO2008/083850 WO 20080717
- Main IPC: H03K9/00
- IPC: H03K9/00

Abstract:
An electronic device comprises a number of sub-systems coupled via an interface. One of the number of sub-systems comprises logic for receiving a frame of input data having a plurality of phases on respective data paths. The electronic device further comprises logic for performing cross correlation on the received input data with a pre-determined bit pattern, operably coupled to selection logic, for selecting a single phase from the plurality of phases sent to the interface to sample the received input data in a middle region of a data bit period in response to the cross correlation.
Public/Granted literature
- US20110142169A1 ELECTRONIC DEVICE, INTEGRATED CIRCUIT AND METHOD FOR SELECTING OF AN OPTIMAL SAMPLING CLOCK PHASE Public/Granted day:2011-06-16
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