发明授权
- 专利标题: Code design and implementation improvements for low density parity check codes for multiple-input multiple-output channels
- 专利标题(中): 用于多输入多输出通道的低密度奇偶校验码的代码设计和实现改进
-
申请号: US12753528申请日: 2010-04-02
-
公开(公告)号: US08392793B2公开(公告)日: 2013-03-05
- 发明人: Mustafa Eroz , Lin-Nan Lee , Feng-Wen Sun
- 申请人: Mustafa Eroz , Lin-Nan Lee , Feng-Wen Sun
- 申请人地址: US CA El Segundo
- 专利权人: DTVG Licensing, Inc.
- 当前专利权人: DTVG Licensing, Inc.
- 当前专利权人地址: US CA El Segundo
- 主分类号: H03M13/00
- IPC分类号: H03M13/00
摘要:
Methods include configuring M parallel accumulation engines, accumulating a first information bit at a first set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each member of the first set of specific parity bit addresses by a pre-determined offset for each new information bit, accumulating subsequent information bits at parity bit addresses that are offset from the specific parity bit addresses by a pre-determined offset until an M+1 information bit is reached, accumulating the next M information bits at a second set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each member of the second set of specific parity bit addresses by the pre-determined offset for each new information bit; and repeating accumulating and increasing the addresses until the information bits are exhausted. Related systems are described.
公开/授权文献
信息查询
IPC分类: