Invention Grant
US08392806B2 Method, device, and digital circuitry for providing a closed-form solution to a scaled error locator polynomial used in BCH decoding
有权
用于为BCH解码中使用的缩放误差定位多项式提供封闭形式解的方法,设备和数字电路
- Patent Title: Method, device, and digital circuitry for providing a closed-form solution to a scaled error locator polynomial used in BCH decoding
- Patent Title (中): 用于为BCH解码中使用的缩放误差定位多项式提供封闭形式解的方法,设备和数字电路
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Application No.: US12846172Application Date: 2010-07-29
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Publication No.: US08392806B2Publication Date: 2013-03-05
- Inventor: Hun-Seok Kim , Seok-Jun Lee , Manish Goel
- Applicant: Hun-Seok Kim , Seok-Jun Lee , Manish Goel
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Steven A. Shaw; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
A method of determining positions of one or more error bits is disclosed. The method includes receiving a BCH codeword at input circuitry of a decoder device, establishing a threshold number of correctable bits, and determining from the received BCH codeword and a root of an encoder polynomial, a value of each of one or more syndromes. The number of the one or more syndromes is twice a maximum number of correctable bits in the received BCH codeword. When the maximum number of correctable bits in the received BCH codeword is less than the threshold number of correctable bits, the value of each coefficient in a scaled error locator polynomial is determined by performing a non-iterative, closed-form solution on the scaled error locator polynomial. The scaled error locator polynomial is an original error locator polynomial scaled by a constant scale factor. The constant scale factor is determined according to the value of each of the one or more syndromes. Having determined the value of each coefficient in the scaled error locator polynomial, one or more roots of the scaled error locator polynomial are obtained. Each of the one or more roots indicates a position of an error bit. A BCH decoder device that can implement the method and a digital circuit that preserves operations implementing the method are also disclosed.
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