- 专利标题： Apparatus, processor and method of cache coherency control
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申请号： US12314492申请日： 2008-12-11
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公开(公告)号： US08397031B2公开(公告)日： 2013-03-12
- 发明人: Yoshiaki Watanabe
- 申请人： Yoshiaki Watanabe
- 申请人地址： JP Kofu-Shi, Yamanashi
- 专利权人： NEC Computertechno, Ltd.
- 当前专利权人： NEC Computertechno, Ltd.
- 当前专利权人地址： JP Kofu-Shi, Yamanashi
- 代理机构： McGinn IP Law Group, PLLC
- 优先权： JP2008-015828 20080128
- 主分类号： G06F12/08
- IPC分类号： G06F12/08
摘要：
An apparatus includes a plurality of processors each of which includes a cache memory, and a controller which suspends a request of at least one of the processors during a predetermined period when a processor fetches a data from a main memory to the cache memory, wherein the controller suspends the request of at least one of the processors except the processor which fetches the data from the main memory to the cache memory.
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