Invention Grant
US08397238B2 Thread allocation and clock cycle adjustment in an interleaved multi-threaded processor
有权
交错多线程处理器中的线程分配和时钟周期调整
- Patent Title: Thread allocation and clock cycle adjustment in an interleaved multi-threaded processor
- Patent Title (中): 交错多线程处理器中的线程分配和时钟周期调整
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Application No.: US12632873Application Date: 2009-12-08
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Publication No.: US08397238B2Publication Date: 2013-03-12
- Inventor: Suresh K. Venkumahanti , Martin Saint-Laurent , Lucian Codrescu , Baker S. Mohammad
- Applicant: Suresh K. Venkumahanti , Martin Saint-Laurent , Lucian Codrescu , Baker S. Mohammad
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Peter M. Kamarchik; Nicholas J. Pauley; Jonathan T. Velasco
- Main IPC: G06F9/46
- IPC: G06F9/46

Abstract:
Methods, apparatuses, and computer-readable storage media are disclosed for reducing power by reducing hardware-thread toggling in a multi-threaded processor. In a particular embodiment, a method allocates software threads to hardware threads. A number of software threads to be allocated is identified. It is determined when the number of software threads is less than a number of hardware threads. When the number of software threads is less than the number of hardware threads, at least two of the software threads are allocated to non-sequential hardware threads. A clock signal to be applied to the hardware threads is adjusted responsive to the non-sequential hardware threads allocated.
Public/Granted literature
- US20110138393A1 Thread Allocation and Clock Cycle Adjustment in an Interleaved Multi-Threaded Processor Public/Granted day:2011-06-09
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