A device architecture for an active matrix display pixel comprising source addressing lines and TFT drain electrode formed on a first metal level of the device, the pixel electrode formed on a second, separate metal level, and the TFT gate electrode and gate addressing lines on a third metal level separated from both the first level and the second level by at least one dielectric layer, wherein the pixel electrode on the second level is electrically connected to the drain electrode on the first level through a via-hole connection and a pixel capacitor is formed by overlap of part of the pixel electrode on the second level with a portion of the gate addressing line of a neighboring line of pixels on the third level. The device is formed preferably using print based methods.