发明授权
US08401019B2 Method, integrated circuit, and communication unit for scheduling a processing of packet stream channels 有权
方法,集成电路和通信单元,用于调度分组流信道的处理

  • 专利标题: Method, integrated circuit, and communication unit for scheduling a processing of packet stream channels
  • 专利标题(中): 方法,集成电路和通信单元,用于调度分组流信道的处理
  • 申请号: US12738421
    申请日: 2007-10-23
  • 公开(公告)号: US08401019B2
    公开(公告)日: 2013-03-19
  • 发明人: Florin-Laurentiu Stoica
  • 申请人: Florin-Laurentiu Stoica
  • 申请人地址: US TX Austin
  • 专利权人: Freescale Semiconductor, Inc.
  • 当前专利权人: Freescale Semiconductor, Inc.
  • 当前专利权人地址: US TX Austin
  • 国际申请: PCT/IB2007/054302 WO 20071023
  • 国际公布: WO2009/053774 WO 20090430
  • 主分类号: H04W4/00
  • IPC分类号: H04W4/00 H04L12/28 H04L12/56
Method, integrated circuit, and communication unit for scheduling a processing of packet stream channels
摘要:
A method for scheduling a processing of packet stream channels comprises: determining whether at least one packet stream channel comprises a frame ready for processing; if at least one packet stream channel comprises a frame ready for processing, identifying a frame ready for processing having a highest priority; and scheduling the identified highest priority frame for processing. The method further comprises prioritising frames ready for processing based on at least one of: a frame availability time and an estimated processing time, for each frame.
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