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US08402181B2 Bifurcate arbiter 有权
分叉仲裁者

Bifurcate arbiter
Abstract:
An arbiter for a space switch comprising a two buffers, a media access controller having data outputs coupled to the two buffers, and two control outputs coupled to respective buffers for buffering input data at a clock rate one-half that of the input data and a switch fabric connected to the two buffers for matching buffer data throughput with switch data throughput, the arbiter comprising first and second schedulers, each scheduler includes a plurality of inputs for connection to the two buffers for receiving requests, a plurality of outputs for granting requests and a plurality of inter connections to each of the plurality of schedulers for informing them of grants and logic for logically grouping input ports associated with a bifurcate input port, logically grouping output ports associated with a bifurcate output port, establishing round robin pointers for each of two alternate clock ticks for tracking next allowable requests and on one clock tick allowing connection requests from input ports to output ports and accepting a connection request in dependence upon the grouping of the input and output ports and the round robin pointer. The arbiter can be generalized to an n-furcated switch having n-furcated ports where n is an integer greater than or equal to two.
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