Invention Grant
- Patent Title: Multi-bit error correction method and apparatus based on a BCH code and memory system
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Application No.: US12704231Application Date: 2010-02-11
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Publication No.: US08402352B2Publication Date: 2013-03-19
- Inventor: Yufei Li , Yong Lu , Ying Wang , Hao Yang
- Applicant: Yufei Li , Yong Lu , Ying Wang , Hao Yang
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Griffiths & Seaton PLLC
- Priority: CN200910007392 20090223
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.
Public/Granted literature
- US20100218068A1 MULTI-BIT ERROR CORRECTION METHOD AND APPARATUS BASED ON A BCH CODE AND MEMORY SYSTEM Public/Granted day:2010-08-26
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