Invention Grant
US08407021B2 Delay analysis device, delay analysis method, and delay analysis program 有权
延迟分析装置,延迟分析方法和延迟分析程序

  • Patent Title: Delay analysis device, delay analysis method, and delay analysis program
  • Patent Title (中): 延迟分析装置,延迟分析方法和延迟分析程序
  • Application No.: US12893362
    Application Date: 2010-09-29
  • Publication No.: US08407021B2
    Publication Date: 2013-03-26
  • Inventor: Noriyuki Ito
  • Applicant: Noriyuki Ito
  • Applicant Address: JP Kawasaki
  • Assignee: Fujitsu Limited
  • Current Assignee: Fujitsu Limited
  • Current Assignee Address: JP Kawasaki
  • Agency: Staas & Halsey LLP
  • Priority: JP2009-231728 20091005
  • Main IPC: G06F19/00
  • IPC: G06F19/00
Delay analysis device, delay analysis method, and delay analysis program
Abstract:
A delay analysis device includes an acquisition section that acquires circuit information relating to a path through which signal propagation can be delayed, a determination section that sets up an assumed fault for each of pins disposed in the path, and determines whether a signal change output from a beginning latch can be propagated to an ending latch for each of pins for which the assumed faults are set up, and an analysis section that calculates a delay distribution by accumulating delay distributions expressed by probability density functions of delays that occur in individual delay elements included in the path determined that a signal change output from the beginning latch can be propagated to the ending latch, and by not accumulating the delay distributions at a pin through which it has been determined that the signal change cannot be propagated to the ending latch based on the acquired circuit information.
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