发明授权
- 专利标题: Checkerboarded high-voltage vertical transistor layout
- 专利标题(中): 棋盘式高压立式晶体管布局
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申请号: US13199792申请日: 2011-09-09
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公开(公告)号: US08410551B2公开(公告)日: 2013-04-02
- 发明人: Vijay Parthasarathy , Sujit Banerjee , Martin H. Manley
- 申请人: Vijay Parthasarathy , Sujit Banerjee , Martin H. Manley
- 申请人地址: US CA San Jose
- 专利权人: Power Integrations, Inc.
- 当前专利权人: Power Integrations, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: The Law Offices of Bradley J. Bereznak
- 主分类号: H01L29/66
- IPC分类号: H01L29/66
摘要:
In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.
公开/授权文献
- US20120061755A1 Checkerboarded high-voltage vertical transistor layout 公开/授权日:2012-03-15
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