Invention Grant
- Patent Title: Advisory system for verifying sensitive circuits in chip-design
- Patent Title (中): 用于验证芯片设计中的敏感电路的咨询系统
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Application No.: US12054195Application Date: 2008-03-24
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Publication No.: US08418098B2Publication Date: 2013-04-09
- Inventor: Chi-Heng Huang , Gary Lin , Chu-Fu Chen , Yi-Kan Cheng , Fu-Lung Hsueh
- Applicant: Chi-Heng Huang , Gary Lin , Chu-Fu Chen , Yi-Kan Cheng , Fu-Lung Hsueh
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H03K5/22
Abstract:
A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits.
Public/Granted literature
- US20090172617A1 Advisory System for Verifying Sensitive Circuits in Chip-Design Public/Granted day:2009-07-02
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