Invention Grant
US08421073B2 Test structures for through silicon vias (TSVs) of three dimensional integrated circuit (3DIC)
有权
三维集成电路（3DIC）的硅通孔（TSV）的测试结构
- Patent Title: Test structures for through silicon vias (TSVs) of three dimensional integrated circuit (3DIC)
- Patent Title (中): 三维集成电路（3DIC）的硅通孔（TSV）的测试结构
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Application No.: US13006639Application Date: 2011-01-14
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Publication No.: US08421073B2Publication Date: 2013-04-16
- Inventor: Hung-Chih Lin , Mill-Jer Wang , Ching-Nen Peng , Hao Chen
- Applicant: Hung-Chih Lin , Mill-Jer Wang , Ching-Nen Peng , Hao Chen
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman Ham & Berner, LLP
- Main IPC: H01L23/58
- IPC: H01L23/58
Abstract:
A plurality of through silicon vias (TSVs) on a substrate or in a 3 dimensional integrated circuit (3DIC) are chained together. TSVs are chained together to increase the electrical signal. A plurality of test pads are used to enable the testing of the TVSs. One of the test pads is grounded. The remaining test pads are either electrically connected to TSVs in the chain or grounded.
Public/Granted literature
- US20120097944A1 TEST STRUCTURES FOR THROUGH SILICON VIAS (TSVs) OF THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) Public/Granted day:2012-04-26
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