发明授权
US08422180B2 High-voltage-tolerant ESD clamp circuit with low leakage current fabricated by low-voltage CMOS process
有权
采用低电压CMOS工艺制造的低漏电流高耐压ESD钳位电路
- 专利标题： High-voltage-tolerant ESD clamp circuit with low leakage current fabricated by low-voltage CMOS process
- 专利标题（中）： 采用低电压CMOS工艺制造的低漏电流高耐压ESD钳位电路
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申请号： US12641037申请日： 2009-12-17
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公开(公告)号： US08422180B2公开(公告)日： 2013-04-16
- 发明人: Chun-Yu Lin , Ming-Dou Ker , Fu-Yi Tsai
- 申请人： Chun-Yu Lin , Ming-Dou Ker , Fu-Yi Tsai
- 申请人地址： TW Science-Based Industrial Park, Hsin-Chu
- 专利权人： Faraday Technology Corp.
- 当前专利权人： Faraday Technology Corp.
- 当前专利权人地址： TW Science-Based Industrial Park, Hsin-Chu
- 代理商 Winston Hsu; Scott Margo
- 主分类号： H02H9/00
- IPC分类号： H02H9/00
摘要：
An electrostatic discharge (ESD) clamp circuit is provided, which includes a plurality of identical module circuits. The anode of the first module circuit is coupled to the cathode of the ESD clamp circuit. The anode of each of the other module circuits is coupled to the cathode of the previous module circuit. The cathode of the last module circuit is coupled to the ground terminal of the ESD clamp circuit. Each module circuit includes a conduction path and a detection circuit. The detection circuit is coupled to the anode, the cathode and the conduction path of the module circuit. When the rising speed of the voltage at the anode of the module circuit surpasses a threshold value, the detection circuit makes the conduction path conducting.
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