发明授权
- 专利标题： Method for integrating a non-volatile memory (NVM)
- 专利标题（中）： 用于集成非易失性存储器（NVM）的方法
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申请号： US12951862申请日： 2010-11-22
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公开(公告)号： US08431471B2公开(公告)日： 2013-04-30
- 发明人: Jane A. Yater , Sung-Taeg Kang , Mehul D. Shroff
- 申请人： Jane A. Yater , Sung-Taeg Kang , Mehul D. Shroff
- 申请人地址： US TX Austin
- 专利权人： Freescale Semiconductor, Inc.
- 当前专利权人： Freescale Semiconductor, Inc.
- 当前专利权人地址： US TX Austin
- 代理商 James L. Cingan, Jr.; Joanna G. Chiu
- 主分类号： H01L21/3205
- IPC分类号： H01L21/3205 ; H01L21/4763
摘要：
A feature is formed in the NVM isolation region during the patterning and etching of an NVM device and a logic device such that the feature is of substantially equal height to the logic device and is well-defined so that it does not cause defect signals. A first conductive layer is formed over a substrate. The first conductive layer is patterned to expose at least a portion of the substrate in an NVM region and at least a portion of an isolation region. An NVM dielectric stack is formed over the first conductive layer, the exposed substrate, and the exposed isolation region, and a second conductive layer is formed over the NVM dielectric stack. The first and second conductive layers and the NVM dielectric stack are patterned to form a first gate and a second gate of an NVM cell in the NVM region and a feature over the isolation region. The feature comprises a portion of the first conductive layer, a portion of the NVM dielectric stack adjacent a first sidewall of the portion of the first conductive layer, and a portion of the second conductive layer adjacent the portion of the NVM dielectric stack.
公开/授权文献
- US20120126309A1 INTEGRATED NON-VOLATILE MEMORY (NVM) AND METHOD THEREFOR 公开/授权日：2012-05-24
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