发明授权
US08438512B2 Method and system for implementing efficient locking to facilitate parallel processing of IC designs
有权
实现有效锁定的方法和系统，以促进IC设计的并行处理
- 专利标题： Method and system for implementing efficient locking to facilitate parallel processing of IC designs
- 专利标题（中）： 实现有效锁定的方法和系统，以促进IC设计的并行处理
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申请号： US13221822申请日： 2011-08-30
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公开(公告)号： US08438512B2公开(公告)日： 2013-05-07
- 发明人: David Cross , Eric Nequist
- 申请人： David Cross , Eric Nequist
- 申请人地址： US CA San Jose
- 专利权人： Cadence Design Systems, Inc.
- 当前专利权人： Cadence Design Systems, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： Vista IP Law Group, LLP
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.
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