- 专利标题： Memory devices having reduced interference between floating gates and methods of fabricating such devices
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申请号： US13180361申请日： 2011-07-11
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公开(公告)号： US08441058B2公开(公告)日： 2013-05-14
- 发明人: Seiichi Aritome
- 申请人： Seiichi Aritome
- 申请人地址： US ID Boise
- 专利权人： Micron Technology, Inc.
- 当前专利权人： Micron Technology, Inc.
- 当前专利权人地址： US ID Boise
- 代理机构： Fletcher Yoder
- 主分类号： H01L29/788
- IPC分类号： H01L29/788
摘要：
A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array.
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