Invention Grant
US08446985B2 Method and system for reducing duty cycle distortion amplification in forwarded clocks
有权
用于减少转发时钟中占空比失真放大的方法和系统
- Patent Title: Method and system for reducing duty cycle distortion amplification in forwarded clocks
- Patent Title (中): 用于减少转发时钟中占空比失真放大的方法和系统
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Application No.: US12343426Application Date: 2008-12-23
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Publication No.: US08446985B2Publication Date: 2013-05-21
- Inventor: Drew G. Doblar , Dawei Huang , Deqiang Song
- Applicant: Drew G. Doblar , Dawei Huang , Deqiang Song
- Applicant Address: US CA Redwood City
- Assignee: Oracle America, Inc.
- Current Assignee: Oracle America, Inc.
- Current Assignee Address: US CA Redwood City
- Agency: Osha Liang LLP
- Main IPC: H03H7/30
- IPC: H03H7/30 ; H03H7/40 ; H03K5/159
Abstract:
A method and apparatus for reducing the amplification of the duty cycle distortion of high frequency clock signals when is provided. A data signal is sent to a receiver via a first channel. A clock signal is sent to the receiver via a second channel. The clock signal is filtered to substantially remove therefrom low frequency components before the clock signal is used by the receiver to recover data from the data signal.
Public/Granted literature
- US20100158182A1 Method and System for Reducing Duty Cycle Distortion Amplification in Forwarded Clocks Public/Granted day:2010-06-24
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