A memory system having a memory card configured to store frame data composed of a plurality of pieces of sector data and a host configured to send and receive the frame data to and from the memory card, the memory card includes: an ECC1 decoder configured to perform BCH decoding processing with a hard decision code on a sector data basis; an ECC2 decoder configured to perform LDPC decoding processing with an LDPC code on a frame data basis; a sector error flag section configured to store information about presence or absence of error data in the BCH decoding processing; and an ECC control section configured to perform, in the LDPC decoding processing, control of increasing a reliability of sector data containing no error data based on the information in the sector error flag section.