Invention Grant
US08452908B2 Low latency serial memory interface 有权
低延迟串行存储器接口

Low latency serial memory interface
Abstract:
A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.
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