Invention Grant
- Patent Title: Low latency serial memory interface
- Patent Title (中): 低延迟串行存储器接口
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Application No.: US12648373Application Date: 2009-12-29
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Publication No.: US08452908B2Publication Date: 2013-05-28
- Inventor: David P. Chengson , Chang-Hong Wu
- Applicant: David P. Chengson , Chang-Hong Wu
- Applicant Address: US CA Sunnyvale
- Assignee: Juniper Networks, Inc.
- Current Assignee: Juniper Networks, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Harrity & Harrity, LLP
- Main IPC: G06F13/14
- IPC: G06F13/14 ; G06F3/00 ; G06F5/00 ; G06F1/04 ; G06F1/12 ; G06F5/06

Abstract:
A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.
Public/Granted literature
- US20110161544A1 LOW LATENCY SERIAL MEMORY INTERFACE Public/Granted day:2011-06-30
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