Invention Grant
- Patent Title: Method for fabricating a connection region in a semiconductor device
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Application No.: US12495578Application Date: 2009-06-30
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Publication No.: US08455326B2Publication Date: 2013-06-04
- Inventor: Sang Soo Lee
- Applicant: Sang Soo Lee
- Applicant Address: KR Icheon-Si
- Assignee: Hynix Semiconductor Inc
- Current Assignee: Hynix Semiconductor Inc
- Current Assignee Address: KR Icheon-Si
- Priority: KR10-2009-0016910 20090227
- Main IPC: H01L21/331
- IPC: H01L21/331

Abstract:
Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a buried-type wordline in an active region defined on a SOI substrate, forming a silicon connection region for connecting an upper silicon layer to a lower silicon layer between neighboring buried type wordlines, and recovering the upper silicon layer on the silicon connection region.
Public/Granted literature
- US20100219473A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Public/Granted day:2010-09-02
Information query
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