Invention Grant
- Patent Title: Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage
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Application No.: US13477431Application Date: 2012-05-22
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Publication No.: US08456922B2Publication Date: 2013-06-04
- Inventor: Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
- Applicant: Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
- Applicant Address: CA Ottawa
- Assignee: MOSAID Technologies Incorporated
- Current Assignee: MOSAID Technologies Incorporated
- Current Assignee Address: CA Ottawa
- Agent Don Mollick
- Main IPC: G11C16/16
- IPC: G11C16/16

Abstract:
A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
Public/Granted literature
- US20120230119A1 WORD LINE DRIVER IN FLASH MEMORY Public/Granted day:2012-09-13
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