发明授权
- 专利标题: Transceiver with latency alignment circuitry
- 专利标题(中): 具有延迟对准电路的收发器
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申请号: US11624966申请日: 2007-01-19
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公开(公告)号: US08458426B2公开(公告)日: 2013-06-04
- 发明人: Kevin Donnelly , Mark Johnson , Chanh Tran , John B. Dillon
- 申请人: Kevin Donnelly , Mark Johnson , Chanh Tran , Nancy D. Dillon
- 申请人地址: US CA Sunnyvale
- 专利权人: Rambus Inc.
- 当前专利权人: Rambus Inc.
- 当前专利权人地址: US CA Sunnyvale
- 主分类号: G06F12/00
- IPC分类号: G06F12/00
摘要:
In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.
公开/授权文献
- US20070118711A1 TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY 公开/授权日:2007-05-24