Invention Grant
US08462887B1 Receiver employing selectable A/D sample clock frequency 有权
接收机采用可选择的A / D采样时钟频率

Receiver employing selectable A/D sample clock frequency
Abstract:
A receiver is set forth that includes a tuner circuit and a converter circuit. The tuner circuit provides an analog signal corresponding to a modulated signal that is received on a selected channel. The converter circuit includes a sample clock that is used to convert the analog signal to a digital signal at a conversion rate corresponding to the frequency of the sample clock. The sample clock is selectable between at least two different clock frequencies.
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