Invention Grant
US08468397B2 Error controlling system, processor and error injection method 有权
错误控制系统,处理器和错误注入方法

  • Patent Title: Error controlling system, processor and error injection method
  • Patent Title (中): 错误控制系统,处理器和错误注入方法
  • Application No.: US12974336
    Application Date: 2010-12-21
  • Publication No.: US08468397B2
    Publication Date: 2013-06-18
  • Inventor: Iwao Yamazaki
  • Applicant: Iwao Yamazaki
  • Applicant Address: JP Kawasaki
  • Assignee: Fujitsu Limited
  • Current Assignee: Fujitsu Limited
  • Current Assignee Address: JP Kawasaki
  • Agency: Staas & Halsey LLP
  • Priority: JP2009-296260 20091225
  • Main IPC: G06F11/00
  • IPC: G06F11/00 H04L1/24
Error controlling system, processor and error injection method
Abstract:
An error controlling system includes a plurality of error generation target circuits, a plurality of pseudo error generating devices each having a pseudo error content holding register that holds directed pseudo error content, each plurality of pseudo error generating device generates a pseudo error corresponding to a pseudo error content held in a respective pseudo error content holding register in at least one of data to be written to one of the plurality of error generation target circuits and data to be read from one of the plurality of error generation target circuits upon being directed to generate the pseudo error, and a pseudo error controlling device that directs the plurality of pseudo error generating devices to generate a pseudo error corresponding to a respective pseudo error content held in each of the pseudo error content holding register provided in each of the plurality of pseudo error generating devices.
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