A system, processor and method are provided for digital signal processing. A processor may initiate processing a sequence of instructions followed by an interrupt. Each instruction may be processed in respective sequential pipeline slots. A branch detector may detect or determine if an instruction is a branch instruction, for example, in turn, for each sequential instruction. In one embodiment, the branch detector may detect if an instruction is a branch instruction until at least a first branch instruction is detected. A processor may annul instructions which are determined to be branch instructions when the interrupt occupies a delay slot associated with the branch instruction. An execution unit may execute at least the sequence of instructions to run a program. The branch detector and/or execution unit may be integral or separate from each other and from the processor.