Invention Grant
- Patent Title: Manufacturing method of flash memory structure with stress area
- Patent Title (中): 具有应力区域的闪存结构的制造方法
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Application No.: US13338405Application Date: 2011-12-28
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Publication No.: US08476156B1Publication Date: 2013-07-02
- Inventor: Yider Wu , Hung-Wei Chen
- Applicant: Yider Wu , Hung-Wei Chen
- Applicant Address: TW
- Assignee: Eon Silicon Solution Inc.
- Current Assignee: Eon Silicon Solution Inc.
- Current Assignee Address: TW
- Agency: Schmeiser, Olsen & Watts LLP
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/4763

Abstract:
In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory.
Public/Granted literature
- US20130171815A1 MANUFACTURING METHOD OF FLASH MEMORY STRUCTURE WITH STRESS AREA Public/Granted day:2013-07-04
Information query
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