Invention Grant
- Patent Title: Configuration of connections in a 3D stack of integrated circuits
- Patent Title (中): 集成电路三维堆叠中的连接配置
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Application No.: US13217789Application Date: 2011-08-25
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Publication No.: US08476771B2Publication Date: 2013-07-02
- Inventor: Michael R. Scheuermann , Joel A. Silberman , Matthew R. Wordeman
- Applicant: Michael R. Scheuermann , Joel A. Silberman , Matthew R. Wordeman
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Louis J. Percello
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L23/48 ; H01L29/40 ; H01L23/02 ; H01L23/538

Abstract:
There is provided a connection configuration for a multiple layer chip stack having two or more strata. Each of the two or more strata has multiple circuit components, a front-side and a back-side. The connection configuration includes a connection pair having as members a front-side connection and a backside connection unconnected to the front-side connection. The front-side connection and the backside connection are co-located with respect to each other on a given stratum from among the two or more strata, and are respectively connected to different ones of the multiple circuit components on the given stratum. At least one of the front-side connection and the backside connection is also connected to a particular one of the multiple circuit components on an adjacent stratum to the given stratum from among the two or more strata.
Public/Granted literature
- US20130049213A1 CONFIGURATION OF CONNECTIONS IN A 3D STACK OF INTEGRATED CIRCUITS Public/Granted day:2013-02-28
Information query
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