- 专利标题: Fabrication of semiconductor interconnect structure
-
申请号: US13116963申请日: 2011-05-26
-
公开(公告)号: US08481432B2公开(公告)日: 2013-07-09
- 发明人: Steven T. Mayer , Daniel A. Koos , Eric Webb
- 申请人: Steven T. Mayer , Daniel A. Koos , Eric Webb
- 申请人地址: US CA Fremont
- 专利权人: Novellus Systems, Inc.
- 当前专利权人: Novellus Systems, Inc.
- 当前专利权人地址: US CA Fremont
- 代理机构: Weaver Austin Villeneuve & Sampson LLP
- 主分类号: H01L21/302
- IPC分类号: H01L21/302
摘要:
An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting. After the metal regions are etched and recessed in the substrate surface, a conductive capping layer is formed using electroless deposition over the recessed exposed metal regions.
公开/授权文献
- US20110223772A1 FABRICATION OF SEMICONDUCTOR INTERCONNECT STRUCTURE 公开/授权日:2011-09-15