Invention Grant
- Patent Title: Wafer-level stack package and method of fabricating the same
- Patent Title (中): 晶圆级堆叠封装及其制造方法
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Application No.: US13027594Application Date: 2011-02-15
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Publication No.: US08482129B2Publication Date: 2013-07-09
- Inventor: In-Young Lee , Ho-Jin Lee , Hyun-Soo Chung , Ju-Il Choi , Son-Kwan Hwang
- Applicant: In-Young Lee , Ho-Jin Lee , Hyun-Soo Chung , Ju-Il Choi , Son-Kwan Hwang
- Applicant Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Consulting, PLLC
- Priority: KR2007-28864 20070323
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.
Public/Granted literature
- US20110147946A1 WAFER-LEVEL STACK PACKAGE AND METHOD OF FABRICATING THE SAME Public/Granted day:2011-06-23
Information query
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