Invention Grant
US08482329B2 High voltage input receiver with hysteresis using low voltage transistors
有权
使用低压晶体管的具有迟滞的高压输入接收器
- Patent Title: High voltage input receiver with hysteresis using low voltage transistors
- Patent Title (中): 使用低压晶体管的具有迟滞的高压输入接收器
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Application No.: US12188227Application Date: 2008-08-08
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Publication No.: US08482329B2Publication Date: 2013-07-09
- Inventor: Vani Deshpande , Anuroop Iyengar , Pramod Elamannu Parameswaran , Pankaj Kumar
- Applicant: Vani Deshpande , Anuroop Iyengar , Pramod Elamannu Parameswaran , Pankaj Kumar
- Applicant Address: US CA San Jose
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA San Jose
- Agency: Mendelsohn, Drucker & Associates, P.C.
- Agent Steve Mendelsohn
- Main IPC: H03K3/00
- IPC: H03K3/00

Abstract:
A high voltage input receiver with hysteresis using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a hysteresis comparator circuit, based on a plurality of low voltage transistors, for generating a first output voltage by comparing an external voltage and a reference voltage and a stress protection circuit for preventing the plurality of low voltage transistors of the hysteresis comparator circuit from exceeding their reliability limits. In addition, the reference voltage is used to set a positive trip point and a negative trip point. Moreover, the input receiver circuit includes a source follower circuit for transferring the first output voltage to an output node of the source follower circuit from a voltage level of a VDDIO to a voltage level of a VDD.
Public/Granted literature
- US20100033214A1 HIGH VOLTAGE INPUT RECEIVER WITH HYSTERESIS USING LOW VOLTAGE TRANSISTORS Public/Granted day:2010-02-11
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