A distributed memory architecture for a layer 2 processing circuit chip (50) is described. In one implementation, the layer 2 processing circuit chip (50) comprises an external memory interface configured to provide access to data packets stored in an external memory (52), a layer 2 processor (54) coupled to the external memory interface (56) and configured to process data packets retrieved from the external memory (56) to generate RLC SDUs, and an on-chip memory (58) coupled to the layer 2 processor (54) and configured to store the RLC PDUs generated by the layer 2 processor (54) prior to their transmission. Upon a request to retransmit an RLC PDU, the layer 2 processor (54) is configured to selectively read the RLC PDU to be retransmitted from the on-chip memory (58) or a data packet comprising the RLC PDU to be retransmitted from the external memory (52). In the latter case, the layer 2 processor (54) is further configured to re-generate the RLC PDU to be retransmitted from the data packet read from the external memory (52). The selectivity of the read operation depends on whether or not the RLC PDU to be retransmitted belongs to a data packet that has been completely transmitted in a single layer 1 transport unit.