Semiconductor devices including buried gate electrodes and isolation layers and methods of forming semiconductor devices including buried gate electrodes and isolation layers using self aligned double patterning

发明授权

US08486818B2 Semiconductor devices including buried gate electrodes and isolation layers and methods of forming semiconductor devices including buried gate electrodes and isolation layers using self aligned double patterning 有权

标题翻译：包括掩埋栅电极和隔离层的半导体器件以及使用自对准双重图案形成半导体器件的方法，包括掩埋栅电极和隔离层

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专利标题： Semiconductor devices including buried gate electrodes and isolation layers and methods of forming semiconductor devices including buried gate electrodes and isolation layers using self aligned double patterning
专利标题（中）： 包括掩埋栅电极和隔离层的半导体器件以及使用自对准双重图案形成半导体器件的方法，包括掩埋栅电极和隔离层
申请号： US12588747

申请日： 2009-10-27
公开(公告)号： US08486818B2

公开(公告)日： 2013-07-16
发明人: Kye-Hee Yeom
申请人： Kye-Hee Yeom
申请人地址： KR Suwon-si, Gyeonggi-do
专利权人： Samsung Electronics Co., Ltd.
当前专利权人： Samsung Electronics Co., Ltd.
当前专利权人地址： KR Suwon-si, Gyeonggi-do
代理机构： Lee & Morse, P.C.
优先权： KR10-2008-0105075 20081027
主分类号： H01L21/76224
IPC分类号： H01L21/76224

Semiconductor devices including buried gate electrodes and isolation layers and methods of forming semiconductor devices including buried gate electrodes and isolation layers using self aligned double patterning

摘要：

A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, and a plurality of buried gate electrodes between a pair of the isolations, wherein each of the buried gate electrodes and the isolations includes a conductive layer and a capping layer.

摘要（中）：

一种半导体器件，包括包括限定半导体衬底的有源区的隔离物的半导体衬底和在一对隔离之间的多个掩埋栅电极，其中每个掩埋栅电极和隔离物包括导电层和覆盖层。

公开/授权文献

US20100102371A1 Semiconductor devices including buried gate electrodes and isolation layers and methods of forming semiconductor devices including buried gate electrodes and isolation layers using self aligned double patterning 公开/授权日：2010-04-29

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