Invention Grant
US08489664B2 Single clock cycle first order limited accumulator for supplying weighted corrections
有权
单时钟周期第一阶有限累加器用于提供加权校正
- Patent Title: Single clock cycle first order limited accumulator for supplying weighted corrections
- Patent Title (中): 单时钟周期第一阶有限累加器用于提供加权校正
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Application No.: US12399861Application Date: 2009-03-06
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Publication No.: US08489664B2Publication Date: 2013-07-16
- Inventor: Viet Linh Do , Wei Fu , Arash Farhoodfar
- Applicant: Viet Linh Do , Wei Fu , Arash Farhoodfar
- Applicant Address: US CA Sunnyvale
- Assignee: Applied Micro Circuits Corporation
- Current Assignee: Applied Micro Circuits Corporation
- Current Assignee Address: US CA Sunnyvale
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
A method is provided for first order accumulation in a single clock cycle. The method accepts a limited gain value and an accumulated value stored in a previous clock cycle. Using combinational logic, the limited gain value is summed with the accumulated value. If the summed value is between upper and lower limits, a non-weighted correction signal is supplied, and the summed value is the storage value. If the summed value is greater than the upper limit, a positive weighting is supplied, the (upper limit+1) is subtracted from the summed value, and the result is the storage value. If the summed value is less than the lower limit, then a negative weighting is supplied, the lower limit is subtracted from the summed value, and the result is the storage value. The storage value is loaded in memory for use as the accumulated value in the subsequent clock cycle.
Public/Granted literature
- US20090172070A1 Single Clock Cycle First Order Limited Accumulator for Supplying Weighted Corrections Public/Granted day:2009-07-02
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