发明授权
US08489862B2 Multiprocessor control apparatus for controlling a plurality of processors sharing a memory and an internal bus and multiprocessor control method and multiprocessor control circuit for performing the same
有权
用于控制共享存储器的多个处理器和内部总线的多处理器控制装置和多处理器控制方法以及用于执行该处理器的多处理器控制电路
- 专利标题： Multiprocessor control apparatus for controlling a plurality of processors sharing a memory and an internal bus and multiprocessor control method and multiprocessor control circuit for performing the same
- 专利标题（中）： 用于控制共享存储器的多个处理器和内部总线的多处理器控制装置和多处理器控制方法以及用于执行该处理器的多处理器控制电路
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申请号： US12663932申请日： 2008-06-05
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公开(公告)号： US08489862B2公开(公告)日： 2013-07-16
- 发明人: Masahiko Saito , Masashige Mizuyama
- 申请人： Masahiko Saito , Masashige Mizuyama
- 申请人地址： JP Osaka
- 专利权人： Panasonic Corporation
- 当前专利权人： Panasonic Corporation
- 当前专利权人地址： JP Osaka
- 代理机构： Wenderoth, Lind & Ponack, L.L.P.
- 优先权： JP2007-154774 20070612
- 国际申请： PCT/JP2008/001438 WO 20080605
- 国际公布： WO2008/152790 WO 20081218
- 主分类号： G06F15/00
- IPC分类号： G06F15/00 ; G06F15/76
摘要：
An object of the invention is to reduce the electric power consumption resulting from temporarily activating a processor requiring a large electric power consumption, out of a plurality of processors. A multiprocessor system (1) includes: a first processor (141) which executes a first instruction code; a second processor (151) which executes a second instruction code, a hypervisor (130) which converts the second instruction code into an instruction code executable by the first processor (141); and a power control circuit (170) which controls the operation of at least one of the first processor (141) and the second processor (151). When the operation of the second processor (151) is suppressed by the power control circuit (170), the hypervisor (130) converts the second instruction code into the instruction code executable by the first processor (141), and the first processor (141) executes the converted instruction code.
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