Invention Grant
US08492272B2 Passivated through wafer vias in low-doped semiconductor substrates
有权
在低掺杂半导体衬底中通过晶片通孔钝化
- Patent Title: Passivated through wafer vias in low-doped semiconductor substrates
- Patent Title (中): 在低掺杂半导体衬底中通过晶片通孔钝化
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Application No.: US13193991Application Date: 2011-07-29
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Publication No.: US08492272B2Publication Date: 2013-07-23
- Inventor: James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Alvin J. Joseph
- Applicant: James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Alvin J. Joseph
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Schmeiser, Olsen & Watts
- Agent Anthony J. Canale
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/04 ; H01L29/40

Abstract:
A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.
Public/Granted literature
- US20130026646A1 PASSIVATED THROUGH WAFER VIAS IN LOW-DOPED SEMICONDUCTOR SUBSTRATES Public/Granted day:2013-01-31
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