Invention Grant
US08492868B2 Method, apparatus, and design structure for silicon-on-insulator high-bandwidth circuitry with reduced charge layer
有权
具有降低电荷层的绝缘体上硅高带宽电路的方法,设备和设计结构
- Patent Title: Method, apparatus, and design structure for silicon-on-insulator high-bandwidth circuitry with reduced charge layer
- Patent Title (中): 具有降低电荷层的绝缘体上硅高带宽电路的方法,设备和设计结构
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Application No.: US12848558Application Date: 2010-08-02
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Publication No.: US08492868B2Publication Date: 2013-07-23
- Inventor: Alan B. Botula , Alvin J. Joseph , James A. Slinkman , Randy L. Wolf
- Applicant: Alan B. Botula , Alvin J. Joseph , James A. Slinkman , Randy L. Wolf
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb & Riley, LLC
- Agent David A. Cain, Esq.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/762

Abstract:
A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.
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